Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of separate conductive lines, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as a “damascene” process. Generally, this process involves forming a via opening in the inter-metal dielectric layer or interlayer dielectric (ILD) between vertically spaced metallization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical mechanical polishing (CMP).
A variant of the above-described process, termed “dual damascene” processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that the contact or via and the upper line are formed simultaneously.
One important technique for implementing damascene processes (as well as other processes) is photolithography, wherein masks are used to transfer circuitry patterns to semiconductor wafers. Typically, a series of such masks are employed in a preset sequence. Each photolithographic mask includes an intricate set of geometric patterns corresponding to the circuit components to be formed on the wafer. Each mask in the series is used to transfer its corresponding pattern onto a photosensitive layer (i.e., a photoresist layer) which has been previously coated on an underlying layer, such as a polysilicon, nitride or metal layer, formed on the silicon wafer. The transfer of the mask pattern onto the photoresist layer is conventionally performed by an optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the mask to expose the photoresist. The photoresist is thereafter developed to form a photoresist mask, and the underlying layer is selectively etched in accordance with the mask to form features such as lines or gates.
Fabrication of the mask follows a set of predetermined design rules set by processing and design limitations. These design rules define the space tolerance between devices and interconnecting lines and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. The design rule limitation is referred to as the critical dimension (“CD”), defined as the smallest width of a line or the smallest space between two lines permitted in the fabrication of the device. The CD for most ultra large scale integration applications is on the order of a fraction of a micron.
As design rules shrink and process windows (i.e., the margins for error in processing) become smaller, inspection and measurement of surface features' CD, as well as their cross-sectional shape (“profile”) are becoming increasingly important. Deviations of a feature's CD and profile from design dimensions may adversely affect the performance of the finished semiconductor device. Furthermore, the measurement of a feature's CD and profile may indicate photolithography problems, such as stepper defocusing and photoresist loss due to overexposure, and/or etch problems such as improper gas flow and magnetic field intensity.
Thus, CD and profile values, and the variation of feature CD from design dimensions, are important indicators of the accuracy and stability of the photoresist and etch processes, and “CD control” to reduce such variation is an important part of semiconductor processing. CD control necessarily involves monitoring and adjusting both the photolithography and etch processes to address CD variations from field to field (FTF) within a wafer, from wafer to wafer (WTW) and from lot to lot (LTL).
Because of the extremely small scale of current CD's, the instrument of choice for measurement and inspection of surface features produced by photolithographic processing, such as dual damascene processing, is a scanning electron microscope (SEM) known as a “critical dimension scanning electron microscope” (CD-SEM). Although conventional SEM's are useful for measuring CD's, they cannot measure some important parameters, such as thickness of a layer to be etched, and they generally do not provide “real time” metrology. In other words, they do not provide immediate feedback to the photolithography process, or feed-forward to the etcher, to reduce LTL variations. SEM measurement is performed “off-line” because it is relatively slow and typically needs to be performed at a separate review station, with inspection results not being known for hours afterward.
Consequently, the results of conventional SEM inspections are not typically used to adjust subsequent etch processing, so the CD measurement of a particular wafer is not used to decide what etch recipe should be used to process that wafer. Rather, the photoresist mask is formed, and then the wafer is etched, assuming that both the mask formation and etching processes are performing within specifications. As a result, yield is typically low due to an undesirably large amount of scrap. Moreover, as wafer sizes increase to 300 mm diameter and larger, the amount of scrap grows exponentially with metrology delays if a process problem occurs. As a further consequence of the inspection necessarily taking place at a physically separate tool, the wafers must be transferred to and from the tool for every inspection performed. This exposes the wafers to the ambient atmosphere, which can result in unwanted oxidation of the wafer surface or deposition of foreign particles on the surface, thereby lowering yield.
Some conventional dual damascene processing includes controlling the dielectric etch step by time or by an in-situ optical means, such as an interferometric sensor, which monitors trench etch in real time. Typically, a sensor in the center of the lid of the etch chamber measures a die average trench depth while the etch process is taking place. However, only trench depth is measured. No profile information is provided by the interferometric sensor, such as trench sidewall angle, notching, or undercutting. Moreover, etch uniformity across the wafer is not monitored by the interferometric sensor, since only the center dies are “seen” by the sensor. Therefore, dies away from the center may be improperly etched, and the interferometric sensor cannot be used to monitor or correct this situation.
There exists a need for a simple, cost-effective methodology for fast and meaningful identification and correction of CD variation without significantly compromising throughput.